The use of refractory metal silicides, and particularly titanium silicide, is becoming a widely accepted practice in very large scale integrated (VLSI) circuits since refractory metal silicides have better conductivity than silicon, thus making them desirable for gates and other interconnections as well as for source/drain regions of the devices.
In the formation of silicides in a single MOS VLSI integrated circuit, it is desirable that the gate electrodes be relatively thick to obtain the full benefit of the high conductivity of the silicide, whereas at the same time it is necessary that the thickness of the silicide in the source/drain regions be thin enough so as to not extend below the doped areas, i.e. not to "punch through" the doped areas which increases the possibility of excessive current leakage. Further, it may be desirable in some cases to have a different metal silicide at the gates than at the source/drain regions. Thus, it is desirable to provide a process which forms the relatively thick high conductivity silicide or similar high conductivity material on the gate electrodes while limiting the thickness of the silicide in the source/drain region so that it does not "punch through" the doped area and also provide for different silicides at different locations.
One approach to providing such differing thicknesses is shown and described in U.S. Pat. No. 4,587,718 assigned to Texas Instruments, Incorporated. This patent, while recognizing the problem, utilizes a technique that does not allow for close control of line width and also utilizes materials which are difficult to accurately and effectively remove during processing without adversely affecting the properties of the integrated circuit chip. Furthermore, these materials compromise in line circuit testing capability.
Other related references include U.S. Pat. No. 4,640,004 assigned to Fairchild Corporation; U.S. Pat. No. 4,746,219 assigned to Texas Instruments, Incorporated; U.S. Pat. No. 4,690,730 assigned to Texas Instruments, Incorporated; the Technical Articles, Morgan et al, Formation of Titanium Nitride/Silicide Bilayers by Rapid Thermal Anneal In Nitrogen, International Electron Devices Meeting, 1985, (Dec. 1-4, 1985) Pages 279 through 287; KU et al., Stable Self-Aligned TiNxOy/TiSi2 Contact Formation For Submicron Device Applications, Appl. Phys. Lett., Vol. 50, NO. 22 (June 1, 1987), pp. 1598-1600; Kaneko, H., et al., Novel Submicron MOS Devices By Self-Aligned Nitridation of Silicide (Sanicide), IEDM 85 (1985), pp. 208-210; U.S. Pat. No. 4,619,038 assigned to Motorola; U.S. Pat. No. 4,593,454 assigned to Societe pour d'Etude et la Fabrication de Circuits Integres Speciaux EFCS; U.S. Pat. No. 4,605,947 assigned to Motorola; U.S. Pat. No. 4,128,670 assigned to IBM. Also see abstract of Japanese Publication Jap. No. 62- 104174 (dated May 14, 1987 and assigned to Nippon Texas Instruments K.K.);